mirror of
https://github.com/danbulant/Cosmos
synced 2026-05-31 13:21:05 +00:00
134 lines
4.7 KiB
C#
134 lines
4.7 KiB
C#
using System;
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using System.Collections.Generic;
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using System.Linq;
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using System.Text;
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namespace Cosmos.Hardware {
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public class ATA {
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protected Core.IOGroup.ATA IO;
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public ATA(Core.IOGroup.ATA aIO) {
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IO = aIO;
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}
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protected void Write(byte channel, byte reg, byte data) {
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//if (reg > 0x07 && reg < 0x0C)
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// ide_write(channel, ATA_REG_CONTROL, 0x80 | channels[channel].nIEN);
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//if (reg < 0x08)
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// outb(data, channels[channel].base + reg - 0x00);
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//else if (reg < 0x0C)
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// outb(data, channels[channel].base + reg - 0x06);
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//else if (reg < 0x0E)
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// outb(data, channels[channel].ctrl + reg - 0x0A);
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//else if (reg < 0x16)
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// outb(data, channels[channel].bmide + reg - 0x0E);
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//if (reg > 0x07 && reg < 0x0C)
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// ide_write(channel, ATA_REG_CONTROL, channels[channel].nIEN);
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}
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[FlagsAttribute]
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enum Status : byte {
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ATA_SR_BSY = 0x80,
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ATA_SR_DRD = 0x40,
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ATA_SR_DF = 0x20,
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ATA_SR_DSC = 0x10,
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ATA_SR_DRQ = 0x08,
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ATA_SR_COR = 0x04,
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ATA_SR_IDX = 0x02,
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ATA_SR_ERR = 0x01
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};
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[FlagsAttribute]
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enum Error : byte {
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ATA_ER_BBK = 0x80,
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ATA_ER_UNC = 0x40,
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ATA_ER_MC = 0x20,
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ATA_ER_IDNF = 0x10,
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ATA_ER_MCR = 0x08,
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ATA_ER_ABRT = 0x04,
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ATA_ER_TK0NF = 0x02,
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ATA_ER_AMNF = 0x01
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};
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enum Cmd : byte {
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ATA_CMD_READ_PIO = 0x20,
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ATA_CMD_READ_PIO_EXT = 0x24,
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ATA_CMD_READ_DMA = 0xC8,
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ATA_CMD_READ_DMA_EXT = 0x25,
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ATA_CMD_WRITE_PIO = 0x30,
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ATA_CMD_WRITE_PIO_EXT = 0x34,
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ATA_CMD_WRITE_DMA = 0xCA,
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ATA_CMD_WRITE_DMA_EXT = 0x35,
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ATA_CMD_CACHE_FLUSH = 0xE7,
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ATA_CMD_CACHE_FLUSH_EXT = 0xEA,
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ATA_CMD_PACKET = 0xA0,
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ATA_CMD_IDENTIFY_PACKET = 0xA1,
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ATA_CMD_IDENTIFY = 0xEC,
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ATAPI_CMD_READ = 0xA8,
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ATAPI_CMD_EJECT = 0x1B
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}
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enum Ident : byte {
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ATA_IDENT_DEVICETYPE = 0,
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ATA_IDENT_CYLINDERS = 2,
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ATA_IDENT_HEADS = 6,
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ATA_IDENT_SECTORS = 12,
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ATA_IDENT_SERIAL = 20,
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ATA_IDENT_MODEL = 54,
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ATA_IDENT_CAPABILITIES = 98,
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ATA_IDENT_FIELDVALID = 106,
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ATA_IDENT_MAX_LBA = 120,
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ATA_IDENT_COMMANDSETS = 164,
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ATA_IDENT_MAX_LBA_EXT = 200
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}
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//#define IDE_ATA 0x00
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//#define IDE_ATAPI 0x01
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//#define ATA_MASTER 0x00
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//#define ATA_SLAVE 0x01
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// Channels:
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//#define ATA_PRIMARY 0x00
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//#define ATA_SECONDARY 0x01
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// Directions:
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//#define ATA_READ 0x00
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//#define ATA_WRITE 0x01
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enum Register : byte {
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ATA_REG_DATA = 0x00,
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ATA_REG_ERROR = 0x01,
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ATA_REG_FEATURES = 0x01,
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ATA_REG_SECCOUNT0 = 0x02,
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ATA_REG_LBA0 = 0x03,
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ATA_REG_LBA1 = 0x04,
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ATA_REG_LBA2 = 0x05,
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ATA_REG_HDDEVSEL = 0x06,
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ATA_REG_COMMAND = 0x07,
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ATA_REG_STATUS = 0x07,
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ATA_REG_SECCOUNT1 = 0x08,
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ATA_REG_LBA3 = 0x09,
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ATA_REG_LBA4 = 0x0A,
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ATA_REG_LBA5 = 0x0B,
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ATA_REG_CONTROL = 0x0C,
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ATA_REG_ALTSTATUS = 0x0C,
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ATA_REG_DEVADDRESS = 0x0D
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// 13 regs
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//* Data Register: BAR0 + 0; // Read-Write
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//* Error Register: BAR0 + 1; // Read Only
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//* Features Register: BAR0 + 1; // Write Only
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//* SECCOUNT0: BAR0 + 2; // Read-Write
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//* LBA0: BAR0 + 3; // Read-Write
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//* LBA1: BAR0 + 4; // Read-Write
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//* LBA2: BAR0 + 5; // Read-Write
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//* HDDEVSEL: BAR0 + 6; // Read-Write, used to select a drive in the channel.
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//* Command Register: BAR0 + 7; // Write Only.
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//* Status Register: BAR0 + 7; // Read Only.
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//* Alternate Status Register: BAR1 + 2; // Read Only.
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//* Control Register: BAR1 + 2; // Write Only.
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//* DEVADDRESS: BAR1 + 2; // I don't know what is the benefit from this register.
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//The map above is the same with the secondary channel, but it uses BAR2 and BAR3 instead of BAR0 and BAR1.
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}
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}
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}
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