mirror of
https://github.com/danbulant/Cosmos
synced 2026-05-27 22:12:25 +00:00
39ab2ac233
Updated Network Card drivers and VMWare SVGA test driver to update and use the Claimed property from above
831 lines
31 KiB
C#
831 lines
31 KiB
C#
using System;
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using System.Collections.Generic;
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using System.Text;
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using Cosmos.Hardware;
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using Cosmos.Kernel;
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namespace Cosmos.Playground.SSchocke
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{
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public class VMWareSVGA
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{
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private enum SVGA_REG
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{
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ID = 0,
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ENABLE = 1,
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WIDTH = 2,
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HEIGHT = 3,
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MAX_WIDTH = 4,
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MAX_HEIGHT = 5,
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DEPTH = 6,
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BITS_PER_PIXEL = 7, /* Current bpp in the guest */
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PSEUDOCOLOR = 8,
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RED_MASK = 9,
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GREEN_MASK = 10,
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BLUE_MASK = 11,
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BYTES_PER_LINE = 12,
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FB_START = 13, /* (Deprecated) */
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FB_OFFSET = 14,
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VRAM_SIZE = 15,
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FB_SIZE = 16,
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/* ID 0 implementation only had the above registers, then the palette */
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CAPABILITIES = 17,
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MEM_START = 18, /* (Deprecated) */
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MEM_SIZE = 19,
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CONFIG_DONE = 20, /* Set when memory area configured */
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SYNC = 21, /* See "FIFO Synchronization Registers" */
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BUSY = 22, /* See "FIFO Synchronization Registers" */
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GUEST_ID = 23, /* Set guest OS identifier */
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CURSOR_ID = 24, /* (Deprecated) */
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CURSOR_X = 25, /* (Deprecated) */
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CURSOR_Y = 26, /* (Deprecated) */
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CURSOR_ON = 27, /* (Deprecated) */
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HOST_BITS_PER_PIXEL = 28, /* (Deprecated) */
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SCRATCH_SIZE = 29, /* Number of scratch registers */
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MEM_REGS = 30, /* Number of FIFO registers */
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NUM_DISPLAYS = 31, /* (Deprecated) */
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PITCHLOCK = 32, /* Fixed pitch for all modes */
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IRQMASK = 33, /* Interrupt mask */
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/* Legacy multi-monitor support */
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NUM_GUEST_DISPLAYS = 34,/* Number of guest displays in X/Y direction */
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DISPLAY_ID = 35, /* Display ID for the following display attributes */
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DISPLAY_IS_PRIMARY = 36,/* Whether this is a primary display */
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DISPLAY_POSITION_X = 37,/* The display position x */
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DISPLAY_POSITION_Y = 38,/* The display position y */
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DISPLAY_WIDTH = 39, /* The display's width */
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DISPLAY_HEIGHT = 40, /* The display's height */
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/* See "Guest memory regions" below. */
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GMR_ID = 41,
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GMR_DESCRIPTOR = 42,
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GMR_MAX_IDS = 43,
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GMR_MAX_DESCRIPTOR_LENGTH = 44,
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TRACES = 45, /* Enable trace-based updates even when FIFO is on */
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TOP = 46, /* Must be 1 more than the last register */
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SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
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/* Next 768 (== 256*3) registers exist for colormap */
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SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768
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/* Base of scratch registers */
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/* Next reg[SCRATCH_SIZE] registers exist for scratch usage:
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First 4 are reserved for VESA BIOS Extension; any remaining are for
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the use of the current SVGA driver. */
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};
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private enum SVGA_CAP
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{
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NONE = 0x00000000,
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RECT_COPY = 0x00000002,
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CURSOR = 0x00000020,
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CURSOR_BYPASS = 0x00000040, // Legacy (Use Cursor Bypass 3 instead)
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CURSOR_BYPASS_2 = 0x00000080, // Legacy (Use Cursor Bypass 3 instead)
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_8BIT_EMULATION = 0x00000100,
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ALPHA_CURSOR = 0x00000200,
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_3D = 0x00004000,
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EXTENDED_FIFO = 0x00008000,
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MULTIMON = 0x00010000, // Legacy multi-monitor support
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PITCHLOCK = 0x00020000,
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IRQMASK = 0x00040000,
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DISPLAY_TOPOLOGY = 0x00080000, // Legacy multi-monitor support
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GMR = 0x00100000,
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TRACES = 0x00200000
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};
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private enum SVGA_FIFO_CAP
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{
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NONE = 0,
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FENCE = 0x01,
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ACCELFRONT = 0x02,
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PITCHLOCK = 0x04,
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VIDEO = 0x08,
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CURSOR_BYPASS_3 = 0x10,
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ESCAPE = 0x20,
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RESERVE = 0x40,
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};
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private enum SVGA_CMD
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{
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INVALID_CMD = 0,
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UPDATE = 1,
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RECT_COPY = 3,
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DEFINE_CURSOR = 19,
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DEFINE_ALPHA_CURSOR = 22,
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UPDATE_VERBOSE = 25,
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FRONT_ROP_FILL = 29,
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FENCE = 30,
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ESCAPE = 33,
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MAX
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};
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private class FifoStruct
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{
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/*struct {
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uint32 reservedSize;
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Bool usingBounceBuffer;
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uint8 bounceBuffer[1024 * 1024];
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uint32 nextFence;
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} fifo;*/
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internal UInt32 reservedSize;
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internal bool usingBounceEffect;
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internal ManagedMemorySpace bounceBuffer;
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internal UInt32 nextFence;
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public FifoStruct()
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{
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this.bounceBuffer = new ManagedMemorySpace(1024 * 1024, 4);
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}
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}
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public class Rect
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{
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public int x, y, w, h;
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public Rect(int xPos, int yPos, int width, int height)
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{
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this.x = xPos;
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this.y = yPos;
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this.w = width;
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this.h = height;
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}
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}
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public class BackBuffer
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{
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public MemoryAddressSpace buffer;
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internal List<Rect> dirtyRecs;
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public BackBuffer()
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{
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dirtyRecs = new List<Rect>();
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}
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public void MarkDirty(Rect r)
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{
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dirtyRecs.Add(new Rect(r.x, r.y, r.w, r.h));
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}
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public Rect[] DirtyRecs
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{
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get { return this.dirtyRecs.ToArray(); }
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}
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internal unsafe void DrawRect(Rect r, uint color)
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{
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uint bytesPerPixel = 4;
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uint bytesPerLine = 1024 * bytesPerPixel;
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for (int y = 0; y < r.h; y++)
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{
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uint offset = (uint)(((r.y + y) * bytesPerLine) + (r.x * bytesPerPixel));
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for (uint x = 0; x < (r.w * bytesPerPixel); x += 4)
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{
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(*(uint*)(buffer.Offset + offset + x)) = color;
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}
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}
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}
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};
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public unsafe class VideoMemoryAddressSpace : MemoryAddressSpace
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{
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public VideoMemoryAddressSpace(UInt32 offset, UInt32 size)
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: base(offset, size)
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{ }
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}
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private PCIDevice pciDev;
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private IOAddressSpace ioBase;
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private MemoryAddressSpace fifoMem;
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public MemoryAddressSpace fbMem;
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private UInt32 fifoSize;
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private UInt32 fbSize;
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private UInt32 deviceVersionID;
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private UInt32 capabilities;
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private UInt32 width;
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private UInt32 height;
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private UInt32 bpp;
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private UInt32 pitch;
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private FifoStruct fifo;
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private const UInt32 SVGA_MAGIC = 0x900000;
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private const UInt32 SVGA_ID_2 = (SVGA_MAGIC << 8) | 2;
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private const UInt32 SVGA_ID_1 = (SVGA_MAGIC << 8) | 1;
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private const UInt32 SVGA_ID_0 = (SVGA_MAGIC << 8) | 0;
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private const UInt32 SVGA_INDEX_PORT = 0x0;
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private const UInt32 SVGA_VALUE_PORT = 0x1;
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private const UInt32 SVGA_IRQSTATUS_PORT = 0x8;
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private const UInt32 SVGA3D_HWVERSION_CURRENT = 2 << 16;
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public static void Test()
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{
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VMWareSVGA vmsvga = null;
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Console.WriteLine("Scanning for VMWare SVGA cards...");
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foreach (PCIDevice device in Cosmos.Hardware.PCIBus.Devices)
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{
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if ((device.VendorID == 0x15AD) && (device.DeviceID == 0x0405) && (device.Claimed == false))
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{
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Console.WriteLine("Found VMWare SVGA on PCI " + device.Bus + ":" + device.Slot + ":" + device.Function);
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Console.WriteLine("VGA IRQ: " + device.InterruptLine);
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vmsvga = new VMWareSVGA(device);
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}
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}
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if (vmsvga == null)
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{
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Console.WriteLine("No VMWare SVGA Adapter found!!");
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return;
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}
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vmsvga.SetMode(1024, 768, 32);
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BackBuffer back = vmsvga.CreateBackBuffer();
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Rect screen = new Rect(0, 0, 1024, 768);
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Rect block = new Rect(100, 100, 100, 100);
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DebugUtil.SendMessage("VMWare", "Screen Rect: r.x=" + screen.x + ", r.y=" + screen.y
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+ ", r.w=" + screen.w + ", r.h=" + screen.h);
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back.buffer.SetMem(0);
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back.MarkDirty(screen);
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vmsvga.SyncBuffers(back);
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uint color = 0xFF333333;
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int ydir = 2;
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int xdir = 2;
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while (true)
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{
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//DebugUtil.SendMessage("VMWare", "BackBuffer: offset=" + back.buffer.Offset + ", size=" + back.buffer.Size);
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//DebugUtil.SendMessage("VMWare", "FrameBuffer: offset=" + vmsvga.fbMem.Offset + ", size=" + vmsvga.fbMem.Size);
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back.DrawRect(block, color);
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back.MarkDirty(block);
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vmsvga.SyncBuffers(back);
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back.DrawRect(block, 0xFF000000);
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back.MarkDirty(block);
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block.x += xdir;
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block.y += ydir;
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if (block.x + block.w >= vmsvga.width)
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{
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xdir *= -1;
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color += 16;
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}
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if (block.y + block.h >= vmsvga.height)
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{
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ydir *= -1;
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color += 16;
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}
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if (block.x <= 0)
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{
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xdir *= -1;
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color += 16;
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}
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if (block.y <= 0)
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{
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ydir *= -1;
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color += 16;
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}
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}
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}
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public VMWareSVGA(PCIDevice dev)
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{
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this.pciDev = dev;
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this.fifo = new FifoStruct();
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ioBase = pciDev.GetAddressSpace(0) as Kernel.IOAddressSpace;
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fbMem = pciDev.GetAddressSpace(1) as MemoryAddressSpace;
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fifoMem = pciDev.GetAddressSpace(2) as Kernel.MemoryAddressSpace;
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// Determine device revision ID
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this.deviceVersionID = SVGA_ID_2;
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do
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{
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writeSVGARegister(SVGA_REG.ID, this.deviceVersionID);
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if (readSVGARegister(SVGA_REG.ID) == this.deviceVersionID)
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{
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break;
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}
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else
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{
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this.deviceVersionID--;
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}
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} while (this.deviceVersionID >= SVGA_ID_0);
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if (this.deviceVersionID < SVGA_ID_0)
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{
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Console.WriteLine("Unsupported Revision of VMWare SVGA adapter!!");
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return;
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}
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this.fbSize = readSVGARegister(SVGA_REG.FB_SIZE);
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this.fifoSize = readSVGARegister(SVGA_REG.MEM_SIZE);
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if (this.fbSize < 0x100000)
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{
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Console.WriteLine("Framebuffer Size too small... something is wrong!!");
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return;
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}
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if (this.fifoSize < 0x20000)
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{
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Console.WriteLine("FIFO Size too small... something is wrong!!");
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return;
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}
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this.pciDev.Claimed = true;
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if (deviceVersionID >= SVGA_ID_1)
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{
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this.capabilities = readSVGARegister(SVGA_REG.CAPABILITIES);
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}
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if ((this.capabilities & (uint)SVGA_CAP.IRQMASK) != 0)
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{
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writeSVGARegister(SVGA_REG.IRQMASK, 0);
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ioBase.Write32(SVGA_IRQSTATUS_PORT, 0xFF);
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Console.WriteLine("Adapter has Interrupt support, but not supported at present by us!!");
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}
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uint fifo_caps = this.fifoMem.Read32(16);
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Console.WriteLine("Adapter Properties: versionID=" + (deviceVersionID & 0xFF) + ", fbSize=" + fbSize
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+ ", fifoSize=" + fifoSize + ", capabilities=" + capabilities + "fifo_cap=" + fifo_caps);
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DebugUtil.SendMessage("VMWare", "Adapter Properties: versionID=" + (deviceVersionID & 0xFF) + ", fbSize=" + fbSize
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+ ", fifoSize=" + fifoSize + ", capabilities=" + capabilities + "fifo_cap=" + fifo_caps);
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}
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public void SetMode(uint width, uint height, uint bpp)
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{
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this.width = width;
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this.height = height;
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this.bpp = bpp;
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writeSVGARegister(SVGA_REG.WIDTH, width);
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writeSVGARegister(SVGA_REG.HEIGHT, height);
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writeSVGARegister(SVGA_REG.BITS_PER_PIXEL, bpp);
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writeSVGARegister(SVGA_REG.ENABLE, 1);
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this.pitch = readSVGARegister(SVGA_REG.BYTES_PER_LINE);
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// Initialize the command FIFO
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this.fifoMem.Write32(0, 1164); // MIN = NUM_REGS * 4
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this.fifoMem.Write32(4, this.fifoSize); // MAX = end of FIFO mem
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this.fifoMem.Write32(8, 1164); // NEXT_CMD = MIN
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this.fifoMem.Write32(12, 1164); // STOP = MIN
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if ((hasFIFOCap(SVGA_CAP.EXTENDED_FIFO) == true) && (isFIFORegValid(1152) == true)) // FIFO_GUEST_3D_HW_VERSION
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{
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fifoMem.Write32(1152, SVGA3D_HWVERSION_CURRENT);// FIFO_GUEST_3D_HW_VERSION
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}
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// Enable the FIFO
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writeSVGARegister(SVGA_REG.CONFIG_DONE, 1);
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this.fbSize = readSVGARegister(SVGA_REG.FB_SIZE);
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this.fifoSize = readSVGARegister(SVGA_REG.MEM_SIZE);
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uint fbOffset = readSVGARegister(SVGA_REG.FB_OFFSET);
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DebugUtil.SendMessage("VMWare", "Adapter Properties: versionID=" + (deviceVersionID & 0xFF) + ", fbSize=" + fbSize
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+ ", fifoSize=" + fifoSize + ", capabilities=" + capabilities + ", fbOffset=" + fbOffset);
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}
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public BackBuffer CreateBackBuffer()
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{
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BackBuffer tmp = new BackBuffer();
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//tmp.buffer = new MemoryAddressSpace(this.fbMem.Offset + (this.width * this.height * (this.bpp / 8)), (this.width * this.height * (this.bpp / 8)));
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tmp.buffer = new ManagedMemorySpace(this.width * this.height * (this.bpp / 8));
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return tmp;
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}
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public void SyncBuffers(BackBuffer back)
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{
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//DebugUtil.SendMessage("VMWare", "Buffer Sync: NumRects=" + back.dirtyRecs.Count);
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for (int rectNum = 0; rectNum < back.dirtyRecs.Count; rectNum++)
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{
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Rect r = back.dirtyRecs[rectNum];
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/*for (int y = 0; y < r.h; y++)
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{
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uint offset = (uint)(((r.y + y) * this.width) + r.x);
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for (uint x = 0; x < r.w; x++)
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{
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fbMem[offset + x] = back.buffer[offset + x];
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}
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}*/
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CopyRect(r, back.buffer);
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//fbMem.CopyFrom(back.buffer);
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update(r);
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}
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back.dirtyRecs.Clear();
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SyncToFence(InsertFence());
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}
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internal unsafe void CopyRect(Rect r, MemoryAddressSpace src)
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{
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uint bytesPerPixel = this.bpp / 8;
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uint bytesPerLine = this.width * bytesPerPixel;
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for (int y = 0; y < r.h; y++)
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{
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uint offset = (uint)(((r.y + y) * bytesPerLine) + (r.x * bytesPerPixel));
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for (uint x = 0; x < (r.w * bytesPerPixel); x++)
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{
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(*(byte*)(fbMem.Offset + offset + x)) = *(byte*)(src.Offset + offset + x);
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//fbMem[offset + x] = back.buffer[offset + x];
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}
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}
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}
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private void SyncToFence(uint fence)
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{
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if (fence == 0)
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{
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DebugUtil.SendError("VMWare", "SyncToFence fence = 0!!");
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return;
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}
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if (!hasFIFOCap(SVGA_FIFO_CAP.FENCE))
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{
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/*
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* Fall back on the legacy sync if the host does not support
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* fences. This is the old sync mechanism that has been
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* supported in the SVGA device pretty much since the dawn of
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* time: write to the SYNC register, then read from BUSY until
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* it's nonzero. This will drain the entire FIFO.
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*
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* The parameter we write to SVGA_REG_SYNC is an arbitrary
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* nonzero value which can be used for debugging, but which is
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* ignored by release builds of VMware products.
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*/
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//DebugUtil.SendMessage("VMWare", "SyncToFence old style sync!!");
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writeSVGARegister(SVGA_REG.SYNC, 1);
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while (readSVGARegister(SVGA_REG.BUSY) != 0) { }
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return;
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}
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if (hasFencePassed(fence))
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{
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return;
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}
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if (isFIFORegValid(1156) && ((this.capabilities & (uint)SVGA_CAP.IRQMASK) != 0))
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{
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// Interrupt based handling of fences... Not supported yet
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}
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//else
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{
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bool busy = true;
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writeSVGARegister(SVGA_REG.SYNC, 1);
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while (hasFencePassed(fence) && busy)
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{
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busy = (readSVGARegister(SVGA_REG.BUSY) != 0);
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}
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}
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if (!hasFencePassed(fence))
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{
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/*
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* This shouldn't happen. If it does, there might be a bug in
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* the SVGA device.
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*/
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DebugUtil.SendError("VMWare", "SyncToFence failed!!");
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}
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}
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private bool hasFencePassed(uint fence)
|
|
{
|
|
if (fence == 0)
|
|
{
|
|
DebugUtil.SendError("VMWare", "hasFencePassed fence = 0!!");
|
|
return true;
|
|
}
|
|
|
|
if (!hasFIFOCap(SVGA_FIFO_CAP.FENCE))
|
|
{
|
|
DebugUtil.SendError("VMWare", "hasFencePassed no FENCE capability!!");
|
|
return false;
|
|
}
|
|
|
|
//DebugUtil.SendMessage("VMWare", "hasFencePassed FIFO_FENCE=" + fifoMem.Read32(24));
|
|
return (((Int32)(fifoMem.Read32(24) - fence)) >= 0);
|
|
}
|
|
|
|
private uint InsertFence()
|
|
{
|
|
if (!hasFIFOCap(SVGA_FIFO_CAP.FENCE))
|
|
{
|
|
return 1;
|
|
}
|
|
|
|
if (fifo.nextFence == 0)
|
|
{
|
|
fifo.nextFence = 1;
|
|
}
|
|
|
|
uint fence = fifo.nextFence++;
|
|
|
|
MemoryAddressSpace cmd = FIFOReserve(8);
|
|
cmd.Write32(0, (uint)SVGA_CMD.FENCE);
|
|
cmd.Write32(4, fence);
|
|
|
|
/*byte[] temp = new byte[8];
|
|
for (uint b = 0; b < temp.Length; b++)
|
|
{
|
|
temp[b] = cmd[b];
|
|
}*/
|
|
//DebugUtil.WriteBinary("VMware", "Fence CMD contents", temp);
|
|
//DebugUtil.SendMessage("VMWare", "SVGA InsertFence: cmd.Offset=" + cmd.Offset + ", cmd.size=" + cmd.Size);
|
|
//DebugUtil.SendMessage("VMWare", "InsertFence fence=" + fence);
|
|
|
|
FIFOCommitAll();
|
|
|
|
return fence;
|
|
}
|
|
|
|
private void update(Rect r)
|
|
{
|
|
MemoryAddressSpace cmd = FIFOReserveCmd(SVGA_CMD.UPDATE, 16);
|
|
|
|
cmd.Write32(4, (uint)r.x);
|
|
cmd.Write32(8, (uint)r.y);
|
|
cmd.Write32(12, (uint)r.w);
|
|
cmd.Write32(16, (uint)r.h);
|
|
|
|
/*byte[] temp = new byte[20];
|
|
for (uint b = 0; b < temp.Length; b++)
|
|
{
|
|
temp[b] = cmd[b];
|
|
}*/
|
|
//DebugUtil.WriteBinary("VMware", "Update CMD contents", temp);
|
|
//DebugUtil.SendMessage("VMWare", "SVGA Update: cmd.Offset=" + cmd.Offset + ", cmd.size=" + cmd.Size);
|
|
|
|
FIFOCommitAll();
|
|
}
|
|
|
|
private void FIFOCommitAll()
|
|
{
|
|
FIFOCommit(fifo.reservedSize);
|
|
}
|
|
|
|
private void FIFOCommit(uint bytes)
|
|
{
|
|
uint min = fifoMem.Read32(0);
|
|
uint max = fifoMem.Read32(4);
|
|
uint nextCmd = fifoMem.Read32(8);
|
|
bool reserveable = hasFIFOCap(SVGA_FIFO_CAP.RESERVE);
|
|
/*DebugUtil.SendMessage("VMWare", "FIFOCommit bytes=" + bytes + ", min=" + min + ", max=" + max
|
|
+ ", nextCmd=" + nextCmd + ", reserveable=" + reserveable + ", usingBounceEffect=" + fifo.usingBounceEffect);*/
|
|
|
|
if (fifo.reservedSize == 0)
|
|
{
|
|
DebugUtil.SendError("VMWare","FIFOCommit before FIFOReserve!!");
|
|
return;
|
|
}
|
|
|
|
fifo.reservedSize = 0;
|
|
|
|
if (fifo.usingBounceEffect)
|
|
{
|
|
/*
|
|
* Slow paths: copy out of a bounce buffer.
|
|
*/
|
|
MemoryAddressSpace buffer = fifo.bounceBuffer;
|
|
if (reserveable)
|
|
{
|
|
/*
|
|
* Slow path: bulk copy out of a bounce buffer in two chunks.
|
|
*
|
|
* Note that the second chunk may be zero-length if the reserved
|
|
* size was large enough to wrap around but the commit size was
|
|
* small enough that everything fit contiguously into the FIFO.
|
|
*
|
|
* Note also that we didn't need to tell the FIFO about the
|
|
* reservation in the bounce buffer, but we do need to tell it
|
|
* about the data we're bouncing from there into the FIFO.
|
|
*/
|
|
|
|
uint chunkSize = Math.Min(bytes, max - nextCmd);
|
|
fifoMem.Write32(54, bytes); // FIFO_RESERVED
|
|
fifoMem.CopyFrom(buffer, 0, nextCmd, chunkSize);
|
|
fifoMem.CopyFrom(buffer, chunkSize, min, bytes - chunkSize);
|
|
}
|
|
else
|
|
{
|
|
/*
|
|
* Slowest path: copy one dword at a time, updating NEXT_CMD as
|
|
* we go, so that we bound how much data the guest has written
|
|
* and the host doesn't know to checkpoint.
|
|
*/
|
|
|
|
uint index = 0;
|
|
while (bytes > 0)
|
|
{
|
|
fifoMem.Write32(nextCmd, buffer.Read32(index));
|
|
nextCmd += 4;
|
|
index += 4;
|
|
if (nextCmd == max)
|
|
{
|
|
nextCmd = min;
|
|
}
|
|
fifoMem.Write32(8, nextCmd); // NEXT_CMD
|
|
bytes -= 4;
|
|
}
|
|
}
|
|
} // if usingBounceEffect
|
|
|
|
// Atomically update NEXT_CMD, if we didn't already
|
|
if ((!fifo.usingBounceEffect) || (reserveable))
|
|
{
|
|
nextCmd += bytes;
|
|
if (nextCmd >= max)
|
|
{
|
|
nextCmd -= (max - min);
|
|
}
|
|
fifoMem.Write32(8, nextCmd); // NEXT_CMD
|
|
}
|
|
|
|
// Clear reservation in the FIFO
|
|
if (reserveable)
|
|
{
|
|
fifoMem.Write32(54, 0);// FIFO_RESERVED
|
|
}
|
|
}
|
|
|
|
private MemoryAddressSpace FIFOReserveCmd(SVGA_CMD type, uint bytes)
|
|
{
|
|
MemoryAddressSpace cmd = FIFOReserve(bytes + 4);
|
|
cmd.Write32(0, (uint)type);
|
|
|
|
return cmd;
|
|
}
|
|
|
|
private MemoryAddressSpace FIFOReserve(uint bytes)
|
|
{
|
|
uint min = fifoMem.Read32(0);
|
|
uint max = fifoMem.Read32(4);
|
|
uint nextCmd = fifoMem.Read32(8);
|
|
bool reserveable = hasFIFOCap(SVGA_FIFO_CAP.RESERVE);
|
|
|
|
/*DebugUtil.SendMessage("VMWare", "FIFOReserve bytes=" + bytes + ", min=" + min + ", max=" + max
|
|
+ ", nextCmd=" + nextCmd + ", reserveable=" + reserveable);*/
|
|
|
|
if ((bytes > fifo.bounceBuffer.Size) || (bytes > (max - min)))
|
|
{
|
|
DebugUtil.SendError("VMWare","FIFO command too large");
|
|
}
|
|
if ((bytes % 4) != 0)
|
|
{
|
|
DebugUtil.SendError("VMWare","FIFO command length not 32-bit aligned");
|
|
}
|
|
if (fifo.reservedSize != 0)
|
|
{
|
|
DebugUtil.SendError("VMWare","FIFOReserve before FIFOCommit");
|
|
}
|
|
|
|
fifo.reservedSize = bytes;
|
|
while (true)
|
|
{
|
|
uint stop = fifoMem.Read32(12);
|
|
bool reserveInPlace = false;
|
|
bool needBounce = false;
|
|
|
|
#region Pick strategy for dealing with data
|
|
if (nextCmd >= stop)
|
|
{
|
|
// No valid FIFO data between nextCmd and max
|
|
if ((nextCmd + bytes < max) || ((nextCmd + bytes == max) && (stop > min)))
|
|
{
|
|
/*
|
|
* Fastest path 1: There is already enough contiguous space
|
|
* between nextCmd and max (the end of the buffer).
|
|
*
|
|
* Note the edge case: If the "<" path succeeds, we can
|
|
* quickly return without performing any other tests. If
|
|
* we end up on the "==" path, we're writing exactly up to
|
|
* the top of the FIFO and we still need to make sure that
|
|
* there is at least one unused DWORD at the bottom, in
|
|
* order to be sure we don't fill the FIFO entirely.
|
|
*
|
|
* If the "==" test succeeds, but stop <= min (the FIFO
|
|
* would be completely full if we were to reserve this
|
|
* much space) we'll end up hitting the FIFOFull path below.
|
|
*/
|
|
reserveInPlace = true;
|
|
//DebugUtil.SendMessage("VMWare", "FIFOReserve Path 1");
|
|
}
|
|
else if ((max - nextCmd) + (stop - min) <= bytes)
|
|
{
|
|
/*
|
|
* We have to split the FIFO command into two pieces,
|
|
* but there still isn't enough total free space in
|
|
* the FIFO to store it.
|
|
*
|
|
* Note the "<=". We need to keep at least one DWORD
|
|
* of the FIFO free at all times, or we won't be able
|
|
* to tell the difference between full and empty.
|
|
*/
|
|
//DebugUtil.SendMessage("VMWare", "FIFOReserve Path 2");
|
|
FIFOFull();
|
|
}
|
|
else
|
|
{
|
|
//DebugUtil.SendMessage("VMWare", "FIFOReserve Path 3");
|
|
needBounce = true;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
// There is FIFO Data between nextCmd and max
|
|
if (nextCmd + bytes < stop)
|
|
{
|
|
/*
|
|
* Fastest path 2: There is already enough contiguous space
|
|
* between nextCmd and stop.
|
|
*/
|
|
reserveInPlace = true;
|
|
//DebugUtil.SendMessage("VMWare", "FIFOReserve Path 4");
|
|
}
|
|
else
|
|
{
|
|
/*
|
|
* There isn't enough room between nextCmd and stop.
|
|
* The FIFO is too full to accept this command.
|
|
*/
|
|
FIFOFull();
|
|
//DebugUtil.SendMessage("VMWare", "FIFOReserve Path 5");
|
|
}
|
|
}
|
|
#endregion
|
|
|
|
// If we decide we can write directly to the FIFO, ensure VM can support this
|
|
if (reserveInPlace)
|
|
{
|
|
if ((reserveable) || (bytes <= 4))
|
|
{
|
|
fifo.usingBounceEffect = false;
|
|
if (reserveable)
|
|
{
|
|
fifoMem.Write32(54, bytes); // FIFO_RESERVED
|
|
//DebugUtil.SendMessage("VMWare", "FIFOReserve in cmd");
|
|
}
|
|
|
|
return new MemoryAddressSpace(fifoMem.Offset + nextCmd, bytes);
|
|
}
|
|
else
|
|
{
|
|
needBounce = true;
|
|
}
|
|
}
|
|
|
|
if (needBounce)
|
|
{
|
|
fifo.usingBounceEffect = true;
|
|
//DebugUtil.SendMessage("VMWare", "FIFOReserve in bounce buffer");
|
|
return fifo.bounceBuffer;
|
|
}
|
|
} // while
|
|
}
|
|
|
|
private void FIFOFull()
|
|
{
|
|
// No support for interrupts yet, so lets just handle it the old way for now
|
|
writeSVGARegister(SVGA_REG.SYNC, 1);
|
|
readSVGARegister(SVGA_REG.BUSY);
|
|
}
|
|
|
|
private void writeSVGARegister(SVGA_REG register, uint value)
|
|
{
|
|
ioBase.Write32(SVGA_INDEX_PORT, (uint)register);
|
|
ioBase.Write32(SVGA_VALUE_PORT, value);
|
|
}
|
|
|
|
private uint readSVGARegister(SVGA_REG register)
|
|
{
|
|
ioBase.Write32(SVGA_INDEX_PORT, (uint)register);
|
|
return ioBase.Read32(SVGA_VALUE_PORT);
|
|
}
|
|
|
|
private bool hasFIFOCap(SVGA_CAP cap)
|
|
{
|
|
return ((this.fifoMem.Read32(16) & (uint)cap) != 0); // Read FIFO_CAPABILITIES to check
|
|
}
|
|
private bool hasFIFOCap(SVGA_FIFO_CAP fifo_cap)
|
|
{
|
|
return ((this.fifoMem.Read32(16) & (uint)fifo_cap) != 0); // Read FIFO_CAPABILITIES to check
|
|
}
|
|
|
|
private bool isFIFORegValid(uint reg)
|
|
{
|
|
return (fifoMem.Read32(0) > reg); // Read FIFO_MIN to check
|
|
}
|
|
}
|
|
}
|