14 commits

Author	SHA1	Message	Date
LostTheBlack_cp	59494f83ae	[+] Added RET instruction.	2008-04-11 15:51:46 +00:00
LostTheBlack_cp	8bd2ce3e31	[*] Fixed RSP index.	2008-04-11 15:15:12 +00:00
LostTheBlack_cp	eb8d1401f3	[!] I've discovered a problem with RSP as index in SIB. Needs to be fixed.	2008-04-11 12:43:21 +00:00
LostTheBlack_cp	70ef86f086	[+] Added some code to support MOV instruction	2008-04-11 11:48:20 +00:00
LostTheBlack_cp	c2cf1cefcb	[+] Every instruction supports converting to FASM code now.	2008-04-11 10:24:33 +00:00
LostTheBlack_cp	8a8cd62a4b	[+] Basic tests passed by all classes.	2008-04-09 11:21:47 +00:00
LostTheBlack_cp	ad77460ba8	[+] push and pop instructions passed tests. ... [*] ModRM, Rex & SIB code is refactored slightly.	2008-04-09 09:22:12 +00:00
LostTheBlack_cp	7a17688f08	[+] Alu dest<-source instructions are almost complete (at least I've no tests that fail)	2008-04-08 16:44:05 +00:00
LostTheBlack_cp	d382dfbdc8	[+] Added some mnemonics for registers. ... [+] Immediate operand instantination.	2008-03-31 11:26:30 +00:00
LostTheBlack_cp	caa4ba3e83	[+] Adc code generation passed some tests. (Reg, Mem and Reg,Reg still not supported)	2008-03-31 11:13:45 +00:00
LostTheBlack_cp	498f293c8a	Added OO-based basic parts of AMD64 jitter: ... [+] Registers enumeration (only GPRs) [+] Basic class ProcessorInstruction [+] Base class InstructionOperand it's child GeneralPurposeRegister [+] Added some abstraction to DestSourceInstruction [+] Added stub for first instruction - AddWithCarry	2008-03-31 06:59:34 +00:00
LostTheBlack_cp	e3a7d7f4dc	[*] Some work on my own test.	2008-03-18 16:16:48 +00:00
LostTheBlack_cp	c1ea0bbb56	[+] My own experimental works.	2008-03-17 14:56:20 +00:00
LostTheBlack_cp	daa82ebf98	I've added my own test project.	2008-03-17 11:03:01 +00:00