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https://github.com/danbulant/Cosmos
synced 2026-06-11 18:51:41 +00:00
Kernels run again :) stupid overflow bug in method footer
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17 changed files with 40 additions and 37 deletions
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@ -15,7 +15,7 @@ namespace Cosmos.Kernel.Plugs.Assemblers {
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//TODO: Do we need to clear rest of EAX first?
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// MTW: technically not, as in other places, it _should_ be working with AL too..
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new CPUx86.Move { DestinationReg = Registers.EAX, SourceValue = 0 };
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new CPUx86.In { Size = 16 };
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new CPUx86.In { DestinationReg = Registers.AX, SourceReg= Registers.DX};
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new CPUx86.Push { DestinationReg = Registers.EAX };
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}
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}
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@ -13,7 +13,7 @@ namespace Cosmos.Kernel.Plugs.Assemblers {
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//TODO: This is a lot of work to read a port. We need to have some kind of inline ASM option that can emit a single out instruction
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//TODO: Also make an attribute that forces normal inlining fo a method
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new CPUx86.Move { DestinationReg = Registers.EDX, SourceReg = Registers.EBP, SourceIsIndirect = true, SourceDisplacement = 0x8 };
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new CPUx86.In { Size = 32 };
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new CPUx86.In { DestinationReg = Registers.EAX, SourceReg = Registers.DX };
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new CPUx86.Push { DestinationReg = Registers.EAX };
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}
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}
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@ -16,7 +16,7 @@ namespace Cosmos.Kernel.Plugs.Assemblers {
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//TODO: Do we need to clear rest of EAX first?
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// MTW: technically not, as in other places, it _should_ be working with AL too..
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new CPUx86.Move { DestinationReg = Registers.EAX, SourceValue=0};
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new CPUNative.In { Size = 8 };
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new CPUNative.In { DestinationReg = Registers.AL, SourceReg = Registers.DX };
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new CPUx86.Push { DestinationReg = Registers.EAX };
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}
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}
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@ -13,7 +13,7 @@ namespace Cosmos.Kernel.Plugs.Assemblers {
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//TODO: This is a lot of work to write to a single port. We need to have some kind of inline ASM option that can emit a single out instruction
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new CPUx86.Move { DestinationReg = Registers.EDX, SourceReg = Registers.EBP, SourceIsIndirect = true, SourceDisplacement = 0xC };
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new CPUx86.Move { DestinationReg = Registers.EAX, SourceReg = Registers.EBP, SourceIsIndirect = true, SourceDisplacement = 0x8 };
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new Out { Size = 16 };
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new Out { DestinationReg = Registers.DX, SourceReg = Registers.AX };
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}
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}
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}
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@ -13,7 +13,7 @@ namespace Cosmos.Kernel.Plugs.Assemblers {
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//TODO: This is a lot of work to write to a single port. We need to have some kind of inline ASM option that can emit a single out instruction
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new CPUx86.Move { DestinationReg = Registers.EDX, SourceReg = Registers.EBP, SourceIsIndirect = true, SourceDisplacement = 0xC };
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new CPUx86.Move { DestinationReg = Registers.EAX, SourceReg = Registers.EBP, SourceIsIndirect = true, SourceDisplacement = 0x8 };
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new Out { Size = 32 };
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new Out { DestinationReg = Registers.DX, SourceReg = Registers.EAX };
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}
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}
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}
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@ -12,7 +12,7 @@ namespace Cosmos.Kernel.Plugs.Assemblers {
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//TODO: This is a lot of work to write to a single port. We need to have some kind of inline ASM option that can emit a single out instruction
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new CPUx86.Move { DestinationReg = Registers.EDX, SourceReg = Registers.EBP, SourceDisplacement = 0xC, SourceIsIndirect = true };
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new CPUx86.Move { DestinationReg = Registers.EAX, SourceReg = Registers.EBP, SourceDisplacement = 0x8, SourceIsIndirect = true };
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new Out { Size = 8 };
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new Out { DestinationReg = Registers.DX, SourceReg = Registers.AL };
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}
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}
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}
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@ -14,17 +14,17 @@ namespace Cosmos.Sys.Plugs.Assemblers
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new CPUx86.Move { DestinationReg = Registers.DX, SourceValue = 0x60 };
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/* Clear all keyboard buffers (output and command buffers) */
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new CPUAll.Label(".clearBuffer");
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new CPUx86.In { Size = 16, DestinationValue = 0x64 };
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new CPUx86.In { DestinationValue = 0x64, SourceReg=Registers.DX };
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new CPUx86.Move { DestinationReg = Registers.AH, SourceReg = Registers.AL };
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new CPUx86.Test { DestinationReg = Registers.AH, SourceValue = 1 };
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new CPUx86.JumpIfZero { DestinationLabel = ".skipClearIO" };
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new CPUx86.In { Size = 16 };
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new CPUx86.In { DestinationReg=Registers.AX, SourceReg=Registers.DX};
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new CPUAll.Label(".skipClearIO");
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new CPUx86.Test { DestinationReg = Registers.AH, SourceValue = 2 };
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new JumpIfNotZero { DestinationLabel = ".clearBuffer" };
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new Move { DestinationReg = Registers.DX, SourceValue = 0x64 };
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new Move { DestinationReg = Registers.AL, SourceValue = 0xfe };
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new Out { Size = 8 };
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new Out {DestinationReg = Registers.DX, SourceReg = Registers.AL };
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new CPUAll.Label(".loop");//failed... halt
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new CPUx86.Halt();
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new CPUx86.Jump { DestinationLabel = ".loop" };
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@ -53,25 +53,25 @@ namespace Indy.IL2CPU.Assembler.X86 {
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// 9600 baud, 8 databits, no parity, 1 stopbit
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new Move { DestinationReg = Registers.DX, SourceValue = (uint)xComAddr + 1 };
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new Move { DestinationReg = Registers.AL, SourceValue = 0 };
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new Out { Size = 8 }; // disable interrupts for serial stuff
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new Out { DestinationReg = Registers.DX, SourceReg = Registers.AL }; // disable interrupts for serial stuff
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new Move { DestinationReg = Registers.DX, SourceValue = (uint)xComAddr + 3 };
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new Move { DestinationReg = Registers.AL, SourceValue = 0x80 };
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new Out { Size = 8 }; // Enable DLAB (set baud rate divisor)
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new Out { DestinationReg = Registers.DX, SourceReg = Registers.AL }; // Enable DLAB (set baud rate divisor)
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new Move { DestinationReg = Registers.DX, SourceValue = (uint)xComAddr };
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new Move { DestinationReg = Registers.AL, SourceValue = 0xC };
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new Out { Size = 8 }; // Set divisor (lo byte)
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new Out { DestinationReg = Registers.DX, SourceReg = Registers.AL }; // Set divisor (lo byte)
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new Move { DestinationReg = Registers.DX, SourceValue = (uint)xComAddr + 1 };
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new Move { DestinationReg = Registers.AL, SourceValue = 0x0 };
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new Out { Size = 8 }; // (hi byte)
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new Out { DestinationReg = Registers.DX, SourceReg = Registers.AL }; // (hi byte)
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new Move { DestinationReg = Registers.DX, SourceValue = (uint)xComAddr + 3 };
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new Move { DestinationReg = Registers.AL, SourceValue = 0x3 };
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new Out { Size = 8 }; // 8 bits, no parity, one stop bit
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new Out { DestinationReg = Registers.DX, SourceReg = Registers.AL }; // 8 bits, no parity, one stop bit
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new Move { DestinationReg = Registers.DX, SourceValue = (uint)xComAddr + 2 };
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new Move { DestinationReg = Registers.AL, SourceValue = 0xC7 };
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new Out { Size = 8 }; // Enable FIFO, clear them, with 14-byte threshold
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new Out { DestinationReg = Registers.DX, SourceReg = Registers.AL }; // Enable FIFO, clear them, with 14-byte threshold
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new Move { DestinationReg = Registers.DX, SourceValue = (uint)xComAddr + 4 };
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new Move { DestinationReg = Registers.AL, SourceValue = 0x3 };
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new Out { Size = 8 }; // IRQ-s enabled, RTS/DSR set
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new Out { DestinationReg = Registers.DX, SourceReg = Registers.AL }; // IRQ-s enabled, RTS/DSR set
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}
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// SSE init
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@ -5,7 +5,7 @@ using System.Text;
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namespace Indy.IL2CPU.Assembler.X86 {
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[OpCode("in")]
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public class In : InstructionWithDestinationAndSourceAndSize {
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public class In : InstructionWithDestinationAndSource {
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public static void InitializeEncodingData(Instruction.InstructionData aData) {
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aData.EncodingOptions.Add(new InstructionData.InstructionEncodingOption {
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OpCode = new byte[] { 0xE4 },
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@ -23,10 +23,5 @@ namespace Indy.IL2CPU.Assembler.X86 {
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DestinationReg=Registers.EAX
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}); // fixed port (register)
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}
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public In() {
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DestinationReg = Registers.EAX;
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SourceReg = Registers.DX;
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}
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}
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}
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@ -5,7 +5,7 @@ using System.Text;
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namespace Indy.IL2CPU.Assembler.X86 {
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[OpCode("out")]
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public class Out: InstructionWithDestinationAndSourceAndSize {
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public class Out: InstructionWithDestinationAndSource {
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public static void InitializeEncodingData(Instruction.InstructionData aData) {
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aData.EncodingOptions.Add(new InstructionData.InstructionEncodingOption {
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OpCode = new byte[] { 0xE6 },
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@ -23,10 +23,5 @@ namespace Indy.IL2CPU.Assembler.X86 {
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DefaultSize=InstructionSize.DWord
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}); // fixed port (register)
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}
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public Out() {
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DestinationReg = Registers.DX;
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SourceReg = Registers.EAX;
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}
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}
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}
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@ -13,5 +13,9 @@ namespace Indy.IL2CPU.Assembler.X86 {
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DestinationImmediateSize=InstructionSize.Word
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});
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}
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public override string ToString() {
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return base.mMnemonic + " " + this.GetDestinationAsString();
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}
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}
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}
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@ -10,7 +10,7 @@ namespace Indy.IL2CPU.Assembler.X86.X {
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return new PortNumber(aPort);
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}
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set {
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new X86.Out { DestinationValue = aPort, Size = 16 };
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new X86.Out { DestinationValue = aPort, SourceReg = Registers.AX };
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}
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}
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@ -19,7 +19,7 @@ namespace Indy.IL2CPU.Assembler.X86.X {
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return new PortNumber(aDX.GetId());
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}
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set {
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new X86.Out { Size = 16 };
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new X86.Out {DestinationReg=Registers.DX, SourceReg=Registers.EAX};
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}
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}
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}
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@ -22,7 +22,7 @@ namespace Indy.IL2CPU.Assembler.X86.X {
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}
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public static implicit operator RegisterAL(PortNumber aValue) {
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new X86.In { Size = 8};
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new X86.In { DestinationReg = Registers.AL, SourceReg = aValue.Register, DestinationValue = aValue.Port };
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return Instance;
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}
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@ -15,7 +15,7 @@ namespace Indy.IL2CPU.IL.X86 {
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var xStackItem_Value = Assembler.StackContents.Pop();
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new CPUx86.Move { DestinationReg = CPUx86.Registers.EBX, SourceValue = 0 };
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new CPUx86.Move { DestinationReg = CPUx86.Registers.CL, SourceReg = CPUx86.Registers.AL };
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new CPUx86.ShiftLeft { DestinationReg = CPUx86.Registers.EDX, SourceReg = CPUx86.Registers.EBX };
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new CPUx86.ShiftLeft { DestinationReg = CPUx86.Registers.EDX, SourceReg = CPUx86.Registers.CL };
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new CPUx86.Push { DestinationReg = CPUx86.Registers.EDX };
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Assembler.StackContents.Push(xStackItem_Value);
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}
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@ -20,7 +20,7 @@ namespace Indy.IL2CPU.IL.X86 {
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new CPUx86.Pop{DestinationReg = CPUx86.Registers.EAX}; // shift amount
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new CPUx86.Pop { DestinationReg = CPUx86.Registers.EBX }; // value
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new CPUx86.Move { DestinationReg = CPUx86.Registers.CL, SourceReg = CPUx86.Registers.AL };
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new CPUx86.ShiftRight { DestinationReg = CPUx86.Registers.EBX };
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new CPUx86.ShiftRight { DestinationReg = CPUx86.Registers.EBX, SourceReg=CPUx86.Registers.CL };
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new CPUx86.Push { DestinationReg = CPUx86.Registers.EBX };
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Assembler.StackContents.Push(xStackItem_Value);
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return;
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@ -33,7 +33,7 @@ namespace Indy.IL2CPU.IL.X86 {
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new CPUx86.JumpIfEqual { DestinationLabel = mLabelName + "__EndLoop" };
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new CPUx86.Move { DestinationReg = CPUx86.Registers.EBX, SourceReg = CPUx86.Registers.ESP, SourceIsIndirect=true };
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new CPUx86.Move { DestinationReg = CPUx86.Registers.CL, SourceValue = 1 };
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new CPUx86.ShiftRight { DestinationReg = CPUx86.Registers.EBX };
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new CPUx86.ShiftRight { DestinationReg = CPUx86.Registers.EBX, SourceReg = CPUx86.Registers.CL };
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new CPUx86.Move { DestinationReg = CPUx86.Registers.ESP, DestinationIsIndirect=true, SourceReg = CPUx86.Registers.EBX };
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new CPUx86.Move { DestinationReg = CPUx86.Registers.CL, SourceValue = 1 };
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new CPUx86.RotateThroughCarryRight { DestinationReg = CPUx86.Registers.ESP, DestinationIsIndirect = true, DestinationDisplacement = 4, Size = 32, SourceReg=CPUx86.Registers.CL };
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@ -98,6 +98,10 @@ namespace Indy.IL2CPU.IL.X86
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}
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new CPUx86.Jump { DestinationLabel = EndOfMethodLabelNameException };
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new Label(EndOfMethodLabelNameException);
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if (Label.LastFullLabel.StartsWith("System_UInt32__Cosmos_Kernel_CPU_GetEndOfKernel")) {
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System.Diagnostics.Debugger.Break();
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}
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//System_UInt32__Cosmos_Kernel_CPU_GetEndOfKernel____DOT__END__OF__METHOD_EXCEPTION
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for (int i = 0; i < aLocAllocItemCount;i++ )
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{
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new CPUx86.Call { DestinationLabel = Label.GenerateLabelName(typeof(RuntimeEngine).GetMethod("Heap_Free")) };
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@ -138,7 +142,11 @@ namespace Indy.IL2CPU.IL.X86
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}
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//new CPUx86.Add(CPUx86.Registers_Old.ESP, "0x4");
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new CPUx86.Pop { DestinationReg = CPUx86.Registers.EBP };
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new CPUx86.Return { DestinationValue = (uint)(aTotalArgsSize - xReturnSize) };
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var xRetSize = ((int)aTotalArgsSize) - ((int)xReturnSize);
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if(xRetSize<0) {
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xRetSize = 0;
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}
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new CPUx86.Return { DestinationValue = (uint)xRetSize };
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}
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}
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}
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@ -1,4 +1,4 @@
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#define BINARY
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//#define BINARY
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using System;
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using System.Collections.Generic;
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using System.Linq;
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@ -12,7 +12,8 @@ namespace TestApp {
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class Program {
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class Renderer : Y86 {
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public void DoRender() {
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new In { Size=32,DestinationReg = Registers.AL, SourceValue=30};
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//new In { Size=32,DestinationReg = Registers.AL, SourceValue=30};
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new Out { DestinationValue = 0x5, SourceReg=Registers.AX};
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}
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}
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static void Main(string[] args) {
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