Kernels run again :) stupid overflow bug in method footer

This commit is contained in:
mterwoord_cp 2008-12-03 07:00:23 +00:00
parent f843b15a6c
commit bf1a830f3f
17 changed files with 40 additions and 37 deletions

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@ -15,7 +15,7 @@ namespace Cosmos.Kernel.Plugs.Assemblers {
//TODO: Do we need to clear rest of EAX first?
// MTW: technically not, as in other places, it _should_ be working with AL too..
new CPUx86.Move { DestinationReg = Registers.EAX, SourceValue = 0 };
new CPUx86.In { Size = 16 };
new CPUx86.In { DestinationReg = Registers.AX, SourceReg= Registers.DX};
new CPUx86.Push { DestinationReg = Registers.EAX };
}
}

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@ -13,7 +13,7 @@ namespace Cosmos.Kernel.Plugs.Assemblers {
//TODO: This is a lot of work to read a port. We need to have some kind of inline ASM option that can emit a single out instruction
//TODO: Also make an attribute that forces normal inlining fo a method
new CPUx86.Move { DestinationReg = Registers.EDX, SourceReg = Registers.EBP, SourceIsIndirect = true, SourceDisplacement = 0x8 };
new CPUx86.In { Size = 32 };
new CPUx86.In { DestinationReg = Registers.EAX, SourceReg = Registers.DX };
new CPUx86.Push { DestinationReg = Registers.EAX };
}
}

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@ -16,7 +16,7 @@ namespace Cosmos.Kernel.Plugs.Assemblers {
//TODO: Do we need to clear rest of EAX first?
// MTW: technically not, as in other places, it _should_ be working with AL too..
new CPUx86.Move { DestinationReg = Registers.EAX, SourceValue=0};
new CPUNative.In { Size = 8 };
new CPUNative.In { DestinationReg = Registers.AL, SourceReg = Registers.DX };
new CPUx86.Push { DestinationReg = Registers.EAX };
}
}

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@ -13,7 +13,7 @@ namespace Cosmos.Kernel.Plugs.Assemblers {
//TODO: This is a lot of work to write to a single port. We need to have some kind of inline ASM option that can emit a single out instruction
new CPUx86.Move { DestinationReg = Registers.EDX, SourceReg = Registers.EBP, SourceIsIndirect = true, SourceDisplacement = 0xC };
new CPUx86.Move { DestinationReg = Registers.EAX, SourceReg = Registers.EBP, SourceIsIndirect = true, SourceDisplacement = 0x8 };
new Out { Size = 16 };
new Out { DestinationReg = Registers.DX, SourceReg = Registers.AX };
}
}
}

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@ -13,7 +13,7 @@ namespace Cosmos.Kernel.Plugs.Assemblers {
//TODO: This is a lot of work to write to a single port. We need to have some kind of inline ASM option that can emit a single out instruction
new CPUx86.Move { DestinationReg = Registers.EDX, SourceReg = Registers.EBP, SourceIsIndirect = true, SourceDisplacement = 0xC };
new CPUx86.Move { DestinationReg = Registers.EAX, SourceReg = Registers.EBP, SourceIsIndirect = true, SourceDisplacement = 0x8 };
new Out { Size = 32 };
new Out { DestinationReg = Registers.DX, SourceReg = Registers.EAX };
}
}
}

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@ -12,7 +12,7 @@ namespace Cosmos.Kernel.Plugs.Assemblers {
//TODO: This is a lot of work to write to a single port. We need to have some kind of inline ASM option that can emit a single out instruction
new CPUx86.Move { DestinationReg = Registers.EDX, SourceReg = Registers.EBP, SourceDisplacement = 0xC, SourceIsIndirect = true };
new CPUx86.Move { DestinationReg = Registers.EAX, SourceReg = Registers.EBP, SourceDisplacement = 0x8, SourceIsIndirect = true };
new Out { Size = 8 };
new Out { DestinationReg = Registers.DX, SourceReg = Registers.AL };
}
}
}

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@ -14,17 +14,17 @@ namespace Cosmos.Sys.Plugs.Assemblers
new CPUx86.Move { DestinationReg = Registers.DX, SourceValue = 0x60 };
/* Clear all keyboard buffers (output and command buffers) */
new CPUAll.Label(".clearBuffer");
new CPUx86.In { Size = 16, DestinationValue = 0x64 };
new CPUx86.In { DestinationValue = 0x64, SourceReg=Registers.DX };
new CPUx86.Move { DestinationReg = Registers.AH, SourceReg = Registers.AL };
new CPUx86.Test { DestinationReg = Registers.AH, SourceValue = 1 };
new CPUx86.JumpIfZero { DestinationLabel = ".skipClearIO" };
new CPUx86.In { Size = 16 };
new CPUx86.In { DestinationReg=Registers.AX, SourceReg=Registers.DX};
new CPUAll.Label(".skipClearIO");
new CPUx86.Test { DestinationReg = Registers.AH, SourceValue = 2 };
new JumpIfNotZero { DestinationLabel = ".clearBuffer" };
new Move { DestinationReg = Registers.DX, SourceValue = 0x64 };
new Move { DestinationReg = Registers.AL, SourceValue = 0xfe };
new Out { Size = 8 };
new Out {DestinationReg = Registers.DX, SourceReg = Registers.AL };
new CPUAll.Label(".loop");//failed... halt
new CPUx86.Halt();
new CPUx86.Jump { DestinationLabel = ".loop" };

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@ -53,25 +53,25 @@ namespace Indy.IL2CPU.Assembler.X86 {
// 9600 baud, 8 databits, no parity, 1 stopbit
new Move { DestinationReg = Registers.DX, SourceValue = (uint)xComAddr + 1 };
new Move { DestinationReg = Registers.AL, SourceValue = 0 };
new Out { Size = 8 }; // disable interrupts for serial stuff
new Out { DestinationReg = Registers.DX, SourceReg = Registers.AL }; // disable interrupts for serial stuff
new Move { DestinationReg = Registers.DX, SourceValue = (uint)xComAddr + 3 };
new Move { DestinationReg = Registers.AL, SourceValue = 0x80 };
new Out { Size = 8 }; // Enable DLAB (set baud rate divisor)
new Out { DestinationReg = Registers.DX, SourceReg = Registers.AL }; // Enable DLAB (set baud rate divisor)
new Move { DestinationReg = Registers.DX, SourceValue = (uint)xComAddr };
new Move { DestinationReg = Registers.AL, SourceValue = 0xC };
new Out { Size = 8 }; // Set divisor (lo byte)
new Out { DestinationReg = Registers.DX, SourceReg = Registers.AL }; // Set divisor (lo byte)
new Move { DestinationReg = Registers.DX, SourceValue = (uint)xComAddr + 1 };
new Move { DestinationReg = Registers.AL, SourceValue = 0x0 };
new Out { Size = 8 }; // (hi byte)
new Out { DestinationReg = Registers.DX, SourceReg = Registers.AL }; // (hi byte)
new Move { DestinationReg = Registers.DX, SourceValue = (uint)xComAddr + 3 };
new Move { DestinationReg = Registers.AL, SourceValue = 0x3 };
new Out { Size = 8 }; // 8 bits, no parity, one stop bit
new Out { DestinationReg = Registers.DX, SourceReg = Registers.AL }; // 8 bits, no parity, one stop bit
new Move { DestinationReg = Registers.DX, SourceValue = (uint)xComAddr + 2 };
new Move { DestinationReg = Registers.AL, SourceValue = 0xC7 };
new Out { Size = 8 }; // Enable FIFO, clear them, with 14-byte threshold
new Out { DestinationReg = Registers.DX, SourceReg = Registers.AL }; // Enable FIFO, clear them, with 14-byte threshold
new Move { DestinationReg = Registers.DX, SourceValue = (uint)xComAddr + 4 };
new Move { DestinationReg = Registers.AL, SourceValue = 0x3 };
new Out { Size = 8 }; // IRQ-s enabled, RTS/DSR set
new Out { DestinationReg = Registers.DX, SourceReg = Registers.AL }; // IRQ-s enabled, RTS/DSR set
}
// SSE init

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@ -5,7 +5,7 @@ using System.Text;
namespace Indy.IL2CPU.Assembler.X86 {
[OpCode("in")]
public class In : InstructionWithDestinationAndSourceAndSize {
public class In : InstructionWithDestinationAndSource {
public static void InitializeEncodingData(Instruction.InstructionData aData) {
aData.EncodingOptions.Add(new InstructionData.InstructionEncodingOption {
OpCode = new byte[] { 0xE4 },
@ -23,10 +23,5 @@ namespace Indy.IL2CPU.Assembler.X86 {
DestinationReg=Registers.EAX
}); // fixed port (register)
}
public In() {
DestinationReg = Registers.EAX;
SourceReg = Registers.DX;
}
}
}

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@ -5,7 +5,7 @@ using System.Text;
namespace Indy.IL2CPU.Assembler.X86 {
[OpCode("out")]
public class Out: InstructionWithDestinationAndSourceAndSize {
public class Out: InstructionWithDestinationAndSource {
public static void InitializeEncodingData(Instruction.InstructionData aData) {
aData.EncodingOptions.Add(new InstructionData.InstructionEncodingOption {
OpCode = new byte[] { 0xE6 },
@ -23,10 +23,5 @@ namespace Indy.IL2CPU.Assembler.X86 {
DefaultSize=InstructionSize.DWord
}); // fixed port (register)
}
public Out() {
DestinationReg = Registers.DX;
SourceReg = Registers.EAX;
}
}
}

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@ -13,5 +13,9 @@ namespace Indy.IL2CPU.Assembler.X86 {
DestinationImmediateSize=InstructionSize.Word
});
}
public override string ToString() {
return base.mMnemonic + " " + this.GetDestinationAsString();
}
}
}

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@ -10,7 +10,7 @@ namespace Indy.IL2CPU.Assembler.X86.X {
return new PortNumber(aPort);
}
set {
new X86.Out { DestinationValue = aPort, Size = 16 };
new X86.Out { DestinationValue = aPort, SourceReg = Registers.AX };
}
}
@ -19,7 +19,7 @@ namespace Indy.IL2CPU.Assembler.X86.X {
return new PortNumber(aDX.GetId());
}
set {
new X86.Out { Size = 16 };
new X86.Out {DestinationReg=Registers.DX, SourceReg=Registers.EAX};
}
}
}

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@ -22,7 +22,7 @@ namespace Indy.IL2CPU.Assembler.X86.X {
}
public static implicit operator RegisterAL(PortNumber aValue) {
new X86.In { Size = 8};
new X86.In { DestinationReg = Registers.AL, SourceReg = aValue.Register, DestinationValue = aValue.Port };
return Instance;
}

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@ -15,7 +15,7 @@ namespace Indy.IL2CPU.IL.X86 {
var xStackItem_Value = Assembler.StackContents.Pop();
new CPUx86.Move { DestinationReg = CPUx86.Registers.EBX, SourceValue = 0 };
new CPUx86.Move { DestinationReg = CPUx86.Registers.CL, SourceReg = CPUx86.Registers.AL };
new CPUx86.ShiftLeft { DestinationReg = CPUx86.Registers.EDX, SourceReg = CPUx86.Registers.EBX };
new CPUx86.ShiftLeft { DestinationReg = CPUx86.Registers.EDX, SourceReg = CPUx86.Registers.CL };
new CPUx86.Push { DestinationReg = CPUx86.Registers.EDX };
Assembler.StackContents.Push(xStackItem_Value);
}

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@ -20,7 +20,7 @@ namespace Indy.IL2CPU.IL.X86 {
new CPUx86.Pop{DestinationReg = CPUx86.Registers.EAX}; // shift amount
new CPUx86.Pop { DestinationReg = CPUx86.Registers.EBX }; // value
new CPUx86.Move { DestinationReg = CPUx86.Registers.CL, SourceReg = CPUx86.Registers.AL };
new CPUx86.ShiftRight { DestinationReg = CPUx86.Registers.EBX };
new CPUx86.ShiftRight { DestinationReg = CPUx86.Registers.EBX, SourceReg=CPUx86.Registers.CL };
new CPUx86.Push { DestinationReg = CPUx86.Registers.EBX };
Assembler.StackContents.Push(xStackItem_Value);
return;
@ -33,7 +33,7 @@ namespace Indy.IL2CPU.IL.X86 {
new CPUx86.JumpIfEqual { DestinationLabel = mLabelName + "__EndLoop" };
new CPUx86.Move { DestinationReg = CPUx86.Registers.EBX, SourceReg = CPUx86.Registers.ESP, SourceIsIndirect=true };
new CPUx86.Move { DestinationReg = CPUx86.Registers.CL, SourceValue = 1 };
new CPUx86.ShiftRight { DestinationReg = CPUx86.Registers.EBX };
new CPUx86.ShiftRight { DestinationReg = CPUx86.Registers.EBX, SourceReg = CPUx86.Registers.CL };
new CPUx86.Move { DestinationReg = CPUx86.Registers.ESP, DestinationIsIndirect=true, SourceReg = CPUx86.Registers.EBX };
new CPUx86.Move { DestinationReg = CPUx86.Registers.CL, SourceValue = 1 };
new CPUx86.RotateThroughCarryRight { DestinationReg = CPUx86.Registers.ESP, DestinationIsIndirect = true, DestinationDisplacement = 4, Size = 32, SourceReg=CPUx86.Registers.CL };

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@ -98,6 +98,10 @@ namespace Indy.IL2CPU.IL.X86
}
new CPUx86.Jump { DestinationLabel = EndOfMethodLabelNameException };
new Label(EndOfMethodLabelNameException);
if (Label.LastFullLabel.StartsWith("System_UInt32__Cosmos_Kernel_CPU_GetEndOfKernel")) {
System.Diagnostics.Debugger.Break();
}
//System_UInt32__Cosmos_Kernel_CPU_GetEndOfKernel____DOT__END__OF__METHOD_EXCEPTION
for (int i = 0; i < aLocAllocItemCount;i++ )
{
new CPUx86.Call { DestinationLabel = Label.GenerateLabelName(typeof(RuntimeEngine).GetMethod("Heap_Free")) };
@ -138,7 +142,11 @@ namespace Indy.IL2CPU.IL.X86
}
//new CPUx86.Add(CPUx86.Registers_Old.ESP, "0x4");
new CPUx86.Pop { DestinationReg = CPUx86.Registers.EBP };
new CPUx86.Return { DestinationValue = (uint)(aTotalArgsSize - xReturnSize) };
var xRetSize = ((int)aTotalArgsSize) - ((int)xReturnSize);
if(xRetSize<0) {
xRetSize = 0;
}
new CPUx86.Return { DestinationValue = (uint)xRetSize };
}
}
}

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@ -1,4 +1,4 @@
#define BINARY
//#define BINARY
using System;
using System.Collections.Generic;
using System.Linq;
@ -12,7 +12,8 @@ namespace TestApp {
class Program {
class Renderer : Y86 {
public void DoRender() {
new In { Size=32,DestinationReg = Registers.AL, SourceValue=30};
//new In { Size=32,DestinationReg = Registers.AL, SourceValue=30};
new Out { DestinationValue = 0x5, SourceReg=Registers.AX};
}
}
static void Main(string[] args) {